Getting to Know…TUB

TU Berlin is participating in the LPGPU2 project through the Embedded Systems Architectures (Architektur eingebetteter Systeme, AES) group of the School of Electrical Engineering and Computer Science. The AES groups investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. Its current research focuses include multi-/many-core architectures and GPUs, development and optimization of highly scalable parallel applications, and (architecture support for) parallel programming models. More information about the AES group is available at http://www.aes.tu-berlin.de/en.

TUB LPGPU2 team (from left to right): Nadjib Mammeri, Sohan Lal, Ben Juurlink, Jana Pilz, Jan Lucas, Biao Wang.

Ben Juurlink – is a Professor at Berlin University of Technology (TU Berlin) and chair of the Embedded Systems Architecture (AES) group at TU Berlin since 2010. He received his PhD in Mathematics and Natural Science (specialization Computer Science and Engineering) from Leiden University, The Netherlands in 1996.

Ben has (co-)authored more than 130 research papers in research fields such as computer architecture, video coding/decoding, and GPU power modeling and estimation.

Ben was the leader of several national projects, work package leader in the European FP6/FP7 projects SARC and Encore, and coordinator of the European H2020 Innovation Action Film265. He was also the coordinator of the FP7 project LPGPU, the successful immediate predecessor of the LPGPU2 project.

Ben also coordinates the LPGPU2 project. He makes sure that the deliverables meet the highest standards and are delivered on time. Ben says of himself that he is a happy and contended coordinator when things run smoothly, but that he can also be mean and nasty when things do not go as expected.

Jan Lucas – has received his diploma in Computer Engineering from TU Berlin in 2009. Before joining TU Berlin and the LPGPU and LPGPU2 projects he has developed secure FPGA-based playback hardware for digital cinema. During the LPGPU1 project he was one of the developers of the GPUSimPow power simulator. He developed a power measurement infrastructure for GPUs and explored alternative GPU architectures.

Jan is currently finishing his PhD at TUB and acts as a LPGPU2 technical lead for TUB. Within the LPGPU2 project he developed the ALUPower data-dependent power model, as well as a new measurement testbed.

Sohan Lal – is a research assistant at TU Berlin. He is also working towards his PhD under the supervision of Prof. Ben Juurlink. He holds an M.Sc. in Information Technology from Indian Institute of Technology, Delhi (IITD).

Sohan developed entropy encoding based memory compression for GPUs and is leading the TUB power model integration task into the LPGPU2 tool. He also worked on LPGPU project which is the predecessor of the LPGPU2 Project. He was co-developer of the GPUSimPow, a GPGPU power simulator and analyzed and identified several performance bottlenecks for GPGPU workloads.

Nadjib – is a research assistant at the Embedded Architecture Group at TU Berlin. He is a hardware engineer by background with a high academic record and an extensive industrial experience gained while working for top tier semiconductor companies. He holds an M.Sc. in Electronic Engineering from Southampton University, UK and a B.Eng in Computer Systems Engineering from Warwick University, UK. He likes adopting new skills, embracing new technologies and working in cross-functional cross-cultural teams. He is fluent in three languages Arabic, English and French and enjoys both playing and watching football.

Biao Wang – received an M.S. degree in Computer Application Technology in 2010 at University of Electronic Science and Technology of China (UESTC), Chengdu, China. Afterward, he joined the Embedded Systems Architecture (AES) group as a PhD student, with a scholarship from China Scholarship Council (CSC). The focus of his doctoral research is high-performance video decoding using Graphic Processing Units (GPUs). He is experienced in exploiting parallelism in H.264 and HEVC decoding on heterogeneous architectures with CPU and GPU devices. As a core developer, he has implemented a highly parallel HEVC CPU+GPU decoder for the application task in the context of LPGPU2.

Jana Pilz – is a secretary at the Embedded Systems Architecture group. She holds a Bachelor degree in German Linguistics and History from Potsdam University, Germany. She also did vocational training as a management assistant in office communication in 1997. She was management assistant for several EU projects, including FP7 project LPGPU, H2020 innovation action project FILM265. She is currently assisting the LPGPU2 project.

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