Author Archives: Mauricio Alvarez-Mesa

Getting to know….Spin Digital

Spin Digital
Spin Digital Video Technologies GmbH (Spin Digital) is a Berlin-based company that develops high-performance video codecs for the next generation immersive media. In the context of LPGPU2 Spin Digital is developing a next generation video rendering engine that combined with Spin Digital’s high performance HEVC decoder allows the creation of advanced media playback applications.

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Spin Digital at NAB 2017

Spin Digital Video Technologies GmbH (Spin Digital) will present an 8K HEVC video solution at NAB 2017. The exhibition will take place from April 24th to 27th at Las Vegas Convention Center –  booth SU14212.

Spin Digital is going to demonstrate a media player capable of processing ultra-high quality video up to 8K using a compact PC-based system. A new 8K monitor will be used to showcase the media player capabilities featuring impressive native 8K content kindly provided by  Spin Digital partners.

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Spin Digital at InterBEE 2016 Japan

Spin Digital Video Technologies GmbH (Spin Digital) will be exhibiting at InterBEE, from November 16th to 18th 2016, at the Makuhari Messe in Tokyo at booth 8209.

Spin Digital will demonstrate a software media player for 4K and 8K. An 8Kp60 playback demo will be presented with GPU and SDI output. A 4Kp60 demo with HDR will be presented as well.

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Spin Digital presents a H.265/HEVC media player with HDR at IBC 2016

Spin Digital Video Technologies GmbH demonstrated at IBC 2016 an end-to-end HDR HEVC/H.265 software solution for ultra-high definition video (4K, 8K, and beyond).  A demonstration was presented at the Amsterdam RAI at Hall 1 Booth 1.F11. Using the HDR-enabled video codec it is possible to encode, decode, and display high quality HDR video using a software solution running on PC platforms.

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Paper accepted at IEEE MMSP 2016

A paper titled  “Efficient HEVC decoder for heterogeneous CPU with GPU systems” authored by B. Wang (TUB), M. Alvarez-Mesa (SD), C. C. Chi (SD), B. Juurlink (TUB), D. F. de Souza, A. Ilic, N. Roma, L. Sousahas been accepted for publication at the IEEE 18th International Workshop on Multimedia Signal Processing (MMSP).

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Spin Digital released a world’s first 8K HEVC/H.265 media player

Berlin, June 2nd 2016: Spin Digital has released a complete software media player supporting 8K HEVC video and 22.2 audio. A demonstration has been presented recently at several international events including NAB in Las Vegas (April 18-21), the “After NAB” show in Tokyo (May 19-20), and the NHK Open House in Tokyo (May 26-29).

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Spin Digital joins LPGPU2

Spin Digital Video Technologies GmbH (Spin Digital), a German company specialized in high-performance video codecs for the next generation of high-quality video applications, has joined LPGPU2, an EU consortium composed of technology companies and universities collaborating on tools for low-power parallel computing using GPUs.

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A Technology Transfer Project has been awarded to AES – TU Berlin and Think Silicon

A technology transfer project called “eGPU accelerated HEVC/H.265 video decoder” has been awarded to AES TU Berlin and Think Silicon. The project is financed by TETRACOM (Technology Transfer in Computing Systems), a coordination action funded by the European Commission under the FP7 program.

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TU Berlin paper to appear at SAMOS XIV

The paper titled “GPGPU Workload Characteristics and Performance Analysis” by Sohan Lal, Jan Lucas, Michael Andersch, Mauricio Alvarez-Mesa, Ahmed Elhossini and Ben Juurlink has been accepted  at SAMOS 2014.

Abstract: GPUs are much more power-efficient devices compared to CPUs, but due to several performance bottlenecks, the performance per watt of GPUs is often much lower than what could be achieved theoretically. To sustain and continue high performance computing growth, new architectural and application techniques are required to create power-efficient computing systems. To find such techniques, however, it is necessary to study the power consumption at a detailed level and understand the bottlenecks which cause low performance. Therefore, in this paper, we study GPU power consumption at component level and investigate the bottlenecks that cause low performance and low energy efficiency.

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TU Berlin Paper to appear at MTAGS13 workshop, Co-located with SC 2013

The paper “FPGA-Based Prototype of Nexus++ Task Manager”, by Tamer Dallou, Ahmed Elhossini and Ben Juurlink, is accepted to appear at the 6th Workshop on Many-Task Computing on Clouds, Grids, and Supercomputers, which is Co-located with Supercomputing/SC 2013, on November 17th, 2013, Denver, Colorado, USA.

The Nexus++ task manager is designed for task-based programming Nexus++_HL2models. Furthermore, it will be ported to GPGPUSim as an extension to add dependency-awareness to GPUs, at block level granularity.

Abstract: StarSs is one of several programming models that try to relieve parallel programming. In StarSs, the programmer has to identify pieces of code that can be executed as tasks, as well as their inputs and outputs. Thereafter, the runtime system (RTS) determines the dependencies between tasks and schedules ready tasks onto worker cores. Previous work has shown, however, that the StarSs RTS may constitute a bottleneck that limits the scalability of the system and proposed a hardware task management system called Nexus++ to eliminate this bottleneck. The first prototype of Nexus++ was implemented in SystemC. Its architecture also had a nondeterministic multi-cycle search algorithm in its critical path, potentially limiting its scalability. In this paper, we improved the architecture of Nexus++ and employed a multi-way set-associative cache-like data structures to optimize its search algorithm and increase task throughput. We also modeled the new architecture in VHDL and targeted a Virtex~5 FPGA from Xilinx. Experimental results show that the new architecture is very resource-efficient utilizing only 19% of the target FPGA. It also shows that Nexus++ achieves a speedup of up to 81x using some synthetic benchmarks modeled after H.264 decoding. Hence, Nexus++ significantly enhances the scalability of applications parallelized using StarSs.

 

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