Hierarchical clustered cache designs are becoming an appealing alternative for multicores. Grouping cores and their caches in clusters reduces network congestion by localizing traffic among several hierarchical levels, potentially enabling much higher scalability. While such architectures can be formed recursively by replicating a base design pattern, keep- ing the whole hierarchy coherent requires more effort and consideration. The reason is that, in hierarchical coherence, even basic operations must be recursive. As a consequence, intermediate-level caches behave both as directories and as leaf caches. This leads to an explosion of states, protocol-races, and protocol complexity. While there have been previ- ous efforts to extend directory-based coherence to hierarchical designs their increased complexity and verification cost is a serious impediment to their adoption.

We aim to address these concerns by encapsulating all hierarchical complexity in a simple function: that of determining when a data block is shared entirely within a cluster (sub-tree of the hierarchy) and is private from the outside. This allows us to eliminate complex recursive operations that span the hierarchy and instead employ simple coherence mechanisms such as self-invalidation and write-through—now restricted to operate within the cluster where a data block is shared.

We examine two inclusivity options and discuss the relation of our approach to the recently proposed Hierarchical-Race-Free (HRF) memory models. Finally, comparisons to both a hierarchical directory-based MOESI and TokenCMP protocols show that, despite its simplicity our approach results in competitive performance and significantly decreased network traffic.

A New Perspective for Efficient Virtual-Cache Coherence. By Stefanos Kaxiras and Alberto Ros.

Accepted to appear in the 40th International Symposium on Computer Architecture (ISCA), 2013.

This paper proposes simple and efficient Coherent shared virtual memory (cSVM) for heterogeneous architectures (CPU + GPU) based on the VIPS coherence technology developed in Uppsala. Coherent shared virtual memory (cSVM) is highly coveted for heterogeneous architectures as it will simplify programming across different cores and manycore accelerators. In this context, virtual L1 caches can be used to great advantage, e.g., saving energy consumption, by eliminating address translation for hits. Unfortunately, multicore virtual-cache coherence is complex and costly because it requires reverse translation for any coherence request directed towards a virtual L1. The reason is the ambiguity of the virtual address due to the possibility of synonyms. In this paper, we take a radically different approach than all prior work which is focused on reverse translation. This results in a new solution for virtual-cache coherence, significantly less complex and more efficient than prior proposals. Significant area, energy, and performance benefits (43.4%, 19.5%, and 5.4%, respectively) ensue as a result of simplifying the entire multicore memory organization, making this the cutting-edge approach for virtualizing the GPU cores.