Author Archives: Jan Lucas – Page 2

TU Berlin at HiPEAC ACACES Summer School 2014

Michael Andersch from TU Berlin will be presenting a poster at this year’s HiPEAC ACACES summer school taking place from 13th to 19th July in Fiuggi, Italy. With the poster entitled “GPGPU Pipeline Latency Analysis”, Michael is showing his work on latency analysis for GPU architectures to the public for the first time. After last year, this is the second time members of TU Berlin’s LPGPU team will be present at ACACES.

“Sparkk: Quality-Scalable Approximate Storage in DRAM” accepted at “The Memory Forum”.

The paper “Sparkk: Quality-Scalable Approximate Storage in DRAM” by Jan Lucas, Mauricio Alvarez Mesa,Michael Andersch and Ben Juurlink has been accepted at The Memory Forum. The Memory Forum 2014 will be held in conjunction with the 41st International Symposium on Computer Architecture (ISCA-41). The paper presents a novel technique for an improved approximative storage area in DRAM.

Update: Paper now online at the Memory Forum.

LPGPU @ Cyber-Physical Systems: Uplifting Europe’s Innovation Capacity

Chris Doran from Geomerics, Daan Nijs from Codeplay, and Ben Juurlink from TU Berlin are currently visiting this two-day event in Brussels which is devoted to explore the innovation potential of Cyber-Physical Systems (CPS). This event is organized by the European Commission and discusses how EU Research and Innovation Programmes can stimulate the creation of new industrial platforms led by EU-actors and facilitate the matchmaking between future user/customer needs and technology offers. For more information, see

Second year reports now available!

The project just finished its second year and again we have some new interesting public reports added to this web page.

The reports tab now has these three additional reports available:

TU Berlin at ACACES.

DART Architecture diagramm

Sohan Lal and Jan Lucas from TU Berlin are going to present two posters at HiPEAC ACACES 2013. The two posters will present some of the most recent research results from the project to the public for the first time.
The poster “Exploring GPGPUs Workload Characteristics and Power Consumption” by Lal et al. will provide interesting insights into the power consumption of GPU workloads and how they are related to the performance characteristics of the workloads.

The poster “DART: A GPU architecture exploiting temporal SIMD for divergent workloads” will present first simulation results for DART, an new GPU architecture developed within the LPGPU consortium by Lucas et al.

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